The field of invention is data conversion, more particularly, this invention relates to multi-step analog-to-digital converters.
1.2 Inventor
Jesper Steensgaard-Madsen, 448 Riverside Drive, apartment # 2, New York, N.Y. 10027, USA, is the sole inventor and applicant. The applicant is a citizen of Denmark.
Highly-linear high-speed analog-to-digital converters (ADCs) are key elements in many electrical systems of great importance. Digital communication systems, e.g., digital-subscriber-line (xDSL) modems, which are capable of providing wide-bandwidth communication via traditional phone lines, are an example of where a system""s overall performance may be limited by the ADC front-end""s finite linearity. The available high-performance ADCs needed for xDSL modems are relatively expensive and will often represent a large fraction of the system""s overall cost. Furthermore, considering that the required good linearity usually is achieved by brute-force calibration of the ADC circuit, the long-term performance reliability may be poor due to aging, ambient temperature variations, and other effects which may cause the circuit""s electrical properties to drift.
2.1 Multi-Step A/D Converters
Multi-step conversion techniques are generally preferred for the implementation of wide-bandwidth high-resolution ADCs. Pipelined multi-step ADCs, hereinafter simply called pipeline ADCs, are generally implemented using switched-capacitor (SC) circuit techniques and may be used for applications with a sampling rate of up to 100 MHz (sometimes even more). Pipeline ADCs"" market share is significant due to the relatively good linearity and bandwidth achievable at a low cost and circuit complexity. FIG. 1 shows a typical 5-step pipeline ADC [50]. The input signal g(t) is sampled at equidistant instances in time (the symbol g(k) represents g(t) for t=k. Tclk, where k is integer and Tclk is the sampling period) and converted into a first coarse (having, say, 3 bits of resolution) digital representation d0(k) by a first flash quantizer [52]. The residue r0(k) of g(k) with respect to d0(k)xc2x7K0, where K0 is the reciprocal of the ADC""s [50] gain, is calculated by the first residue stage [54]. In the ideal case, the following relationship will result: g(k)=d0(k)xc2x7K0+r0(k). The objective is to generate an estimate dr0(k) of r0(k)/K0, whereby an estimate d0(k) of g(k)/K0 can be easily calculated: dg(k)=d0(k)+dr0(k). In other words, dr0(k) compensates for the residue r0(k) of the first-stage quantization d0(k), i.e., the system [50] is a multi-step residue-compensating ADC.
Gain Scaling.
An amplified version A0Axc2x7r0(k), rather than r0(k) itself, is quantized to A0Dxc2x7dr0(k), where nominally A0A=A0D=A0. The analog-domain amplification, A0A, can easily be made an integral part of the residue stage [54] (discussed below). The advantage of amplifying the analog signal level by A0 is that noise, offset, and all other errors from the residue quantizer [58], will be suppressed by 1/A0 when referred to the output signal dg(k). It is thus preferable to make A0 large. How large A0 can be made depends on the magnitude of r0(k) relative to the residue quantizer""s [58] full-scale range, i.e., A0 will largely be proportional to the resolution of d0(k).
Digital Correction.
FIG. 2 shows an example of a typical nominal characteristic of 4 r0(k) as a function of g(k) when using a 5-level flash quantizer [52]. It is assumed that the overall pipeline ADC [50D], as well as the residue quantizer [58], is able to resolve their respective input signals in a range from xe2x88x92Vref to +Vref. Notice that the chosen gain factor A0=4, in principle, can be increased from 4 to 5. However, choosing A0 as the nominally largest possible value is not recommendable because the flash quantizer [52] will generally be subject to substantial imperfections/nonlinearities, in which case the amplified residue signal 4xc2x7r0(k) rather will be described by the qualitative characteristic shown in FIG. 3. It is a key point that the overall operation will be robust with respect to all errors from the flash quantizer [52], provided that A0xc2x7r0(k) is calculated correctly and the residue quantizer [58] is not overloaded. The concept of deliberately under designing the residue stage""s [54] gain factor, A0, is usually called for xe2x80x9cdigital correction.xe2x80x9d Because it is a very simple and low-cost way to avoid potentially large nonlinearities due to displacement of the flash quantizer""s [52] threshold voltages, digital correction is used extensively in essentially all modern pipeline ADCs.
Pipelining.
Consider again FIG. 1. From a simplistic point of view (i.e., when neglecting the impact of digital correction), d0(k) is the most significant digit and dr0(k) the least significant digits of dg(k) represented in a number system which is not necessarily the Arabian base-10 system. Thus, a pipeline ADC [50] may be construed as a system that digitizes the input signal g(k) sequentially one digit at a time (here, for simplicity, assuming that all signals have the same resolution, which need not be the case): d0(k), d1(k), d2(k), d3(k), and then d4(k). To allow a high sampling rate, the determination of the individual digits is spread over several clock cycles and separate circuit stages. In other words, the first stage [56] determines the most-significant digit of the most recent sample of g(k), while the residue quantizer [58] determines the less-significant digits in the four previous samples (one digit per input sample per clock cycle). It is, therefore, necessary to delay individually the digit signals, d0(k), d1(k), d2(k), d3(k), and d4(k), such that the digits representing the same input sample are combined to form one sample of dg(k). The technique of staggering in time and spreading over several circuit stages the determination of the individual digits is called xe2x80x9cpipelining.xe2x80x9d
Implementation.
FIG. 4 shows a simplified representation of the pipeline ADC [50] from FIG. 1; the simplification lies only in the more compact representation of the residue quantizer [58]. This simplified representation is particularly useful if the gain factor A0 is relatively high, in which case the subsequent quantizer [58] often can be modeled by an ideal one when evaluating the overall performance. In fact, the residue quantizer [58] is often designed using second-grade circuitry with low power consumption, such that its linearity is only as good as necessary. Assuming that this assumption is justifiable, and that digital correction is used wisely, it may be concluded that the errors that will limit the ADC""s [50] performance will originate from imperfections in the first residue stage [54].
FIG. 5 shows how the input stage [56] can be implemented efficiently. The flash quantizer [52] is based on an array of latches [60] (for simplicity, only four latches [60] are shown, although the use of 8, 16, or even 32 latches generally is preferable) and a resistor ladder [62] generating the latches"" [60] nominal threshold voltages. Four boolean signals, x0, x1, x2, and x3, generated when strobing the latches [60] represent d0(k) in a so-called thermometer code.
The DAC is implemented by a voltage buffer [64], buffering each of the four boolean signals to plus/minus the reference voltage (xc2x1Vref), and an array of nominally identical capacitors [66]. The DAC capacitors [66] and the gain-scaling capacitor [68] also sample the input signal""s g(t) value g(k) when the sampling switch [70] is opened at the end of clock phase "PHgr"1, at which time the flash quantizer [52] is also strobed. The non-overlapping periodic clock phases are shown in FIG. 6. The residue signal r0(k) is represented by the operational amplifier""s [72] (opamp""s) output voltage at the end of clock phases "PHgr"2. The gain factor A0, which here is set to be 4, is determined by one plus the ratio of the DAC capacitors"" [66] total capacitance divided by the gain-scaling capacitor""s [68] capacitance.
Linearity.
It is assumed that the reference voltages, xc2x1Vref, are well-regulated, which is achievable when using proper circuit techniques. DAC nonlinearity can thus be caused only by mutual mismatch of the nominally identical DAC capacitors [66], which in a traditional pipeline ADC [50] generally will be the dominating source of nonlinear errors. The DAC""s linearity will largely be inversely proportional to the relative standard deviation "sgr"DAC/CDAC of the DAC capacitors"" [66] total capacitance CDAC FIG. 7 shows the fast-Fourier transformed (FFT) of dg(k), when g(k) is a full-scale two-tone signal in the neighborhood of {fraction (1/10)} of the Nyquist frequency; only thermal noise from the sampling operation and mismatch of the DAC capacitors [66] have been accounted for in this simulation. The Figure is based on an estimated value of "sgr"DAC/CDAC=0.00038 for CDAC=1 pF (pico-Farad), which is a representative value for many modern CMOS technologies.
Spurious tones, i.e., harmonic and intermodulation distortion, with a power of up to about xe2x88x9277 dB relative to Vref2, are observed. It should be understood that FIG. 7 shows the frequency spectrum obtained by averaging of several experiments based on the same stochastic process. The performance of the worst ADCs from a production with a 99% yield will be about 10 dB worse. In other words, 20log10("PHgr"DAC/CDAC)≅68 dB, which corresponds to an effective linearity of about 11 bits, is a more realistic estimate of the worst-case linearity of the considered pipeline ADC circuit [50] with a reasonable yield.
It is a fundamental statistical property, which is valid for virtually any technology when using good layout techniques and CDAC is not too small, that "PHgr"DAC/CDAC will be inversely proportional to {square root over (CDAC)}. Hence, the ADC""s effective linearity can be improved by, say, 3 bits simply by increasing CDAC by a factor of 64. Unfortunately, in doing so, the circuit""s power consumption will also be increased by the same factor of 64. Hence, increasing CDAC is not a very attractive way to improve the linearity, especially not for ADCs intended for use in battery-powered equipment. Mismatch of A0A and A0D (or equivalently, mismatch of K0 and K1) is another potential source of significant nonlinearities. A gain-mismatch-induced error             d      e        ⁢          (      k      )        =                              r          0                ⁢                  (          k          )                            K        0              ·          [                                                  A                              0                ⁢                A                                                    A                              0                ⁢                D                                              ⁢                                    K              0                                      K              1                                      -        1            ]      
will be comprised in the output signal dg(k). Considering that de(k) and r0(k) are proportional, and that r0(k) is a highly-nonlinear function of g (k) (see FIGS. 2 and 3) it is concluded that the magnitude of de(k) should be at most one least-significant bit. The magnitude of de(k) can be reduced by reducing the magnitude of r0(k), i.e., by increasing the first flash quantizer""s [52] resolution, or by reducing the mismatch factor: (A0A/A0D)xc2x7(K0/K1)xe2x88x921. The effect of the DAC-gain mismatch factor, K0/K1, will usually be very small and can be neglected. Thus, the 3"sgr"-value of the mismatch factor will be approximately {square root over (A0)}xc2x73xc2x7"sgr"DAC/CDAC. Defining N as the first-stage flash quantizer""s resolution in levels, it follows that the relative magnitude of r0(k) is 1/N. Hence, errors due to mismatch of the DAC capacitors [66] will generally be the dominating source of nonlinear errors if N is 9 or greater. However, if the errors due to mismatch of the DAC capacitors [66] somehow can be eliminated (which is one aspect of this invention), it follows that N will have to be impractically large to achieve an effective linearity of, say, 14 bits or more, unless CDAC is very large.
Analog-to-digital converters implemented according to this invention comprise a first dithered quantizer generating a first estimate d0(k) of the analog input signal, a compensation stage generating a compensation signal dr0(k), and a digital circuit combining d0(k) and dr0(k) to form an output signal dg(k) representing the analog input signal.
3.1 Objects and Advantages
Accordingly, several objects and advantages of this invention are:
to provide low-cost highly-linear analog-to-digital converters (ADCs) suitable for use in demanding systems, such as audio applications and xDSL modems;
to provide highly-linear ADCs, the linearity of which do not rely on highly-accurate matching or control of electrical parameters;
to provide highly-linear ADCs with a low power consumption;
to provide highly-linear ADCs with a wide bandwidth;
to provide ADCs with a good long-term performance reliability;
to provide ADCs which are comparable to pipeline ADCs in terms of circuit complexity, but which have a superior linearity;
to provide highly-accurate wide-bandwidth ADCs, for which the robustness to mismatch, including mismatch of transfer functions, is very good;
to provide ADCs where dominating nonlinearities are made subject to a stochastic process converting harmonic and intermodulation distortion into a noise-like error signal, which generally is preferable in comparison to deterministic errors (i.e., distortion);
to provide ADCs optimized with respect to the environment in which digital-subscriber-line modems operate;
to provide ADCs which are optimized for the conversion of signals (as opposed to the conversion of an uncorrelated stream of data), which is the cornerstone of many digital communication systems.
to provide ADCs which can tolerate more latch latency than traditional pipeline ADCs, thereby increasing the maximum sampling rate and reducing the bit-error-rate;
to provide a multi-step A/D conversion technique where the input signal g(t) is not sampled at the input, which allows for a superior noise performance.
Further objects and advantages will become apparent from a consideration of the ensuing description, the drawings, and the claims.